S-100 Serial cards
Additional notes on the various UARTs ans USARTs used on the S-100 Serial cards [TOP]
Common Types:
6850 ACIA, Motorola [pdf]
Asynchronous communications interface adapter
6850 is a 1 MHz speed
68A50 is a 1.5 MHz speed
68B50 is a 2 MHz speed
used on the Altair SIO
24-pin DIP
8251, Intel [pdf]6850 is a 1 MHz speed
68A50 is a 1.5 MHz speed
68B50 is a 2 MHz speed
used on the Altair SIO
24-pin DIP
Programmable communication interface
Asynchronous and synchronous operation
Compatible with 9551,2651
built in Baud Rate Generator
28-pin DIP package
8251A is capable of 4MHz operation
9551, AMD [pdf]Asynchronous and synchronous operation
Compatible with 9551,2651
built in Baud Rate Generator
28-pin DIP package
8251A is capable of 4MHz operation
Programmable communication interface
Asynchronous and synchronous operation
Compatible with 8251,2651
built in Baud Rate Generator
28-pin DIP package
9551 is capable of 6MHz operation
2651, Signetics [pdf]Asynchronous and synchronous operation
Compatible with 8251,2651
built in Baud Rate Generator
28-pin DIP package
9551 is capable of 6MHz operation
Potential difficulties with the 9551:
The only serious problem with the USART concerned transmit shutdown. When the contents of a data packet have been sent to a port, it is necessary to shutdown transmission mode. Neither the UART nor the USART have the ability to transmit an invisible idle (ASCII rubout with start bit omitted or set to mark).When the Transmit is disabled, it simply blocked the path from the UART. With the AMD 9551, turning off transmit mode had two effects. One was to disable future character requests. The second effect was to immediately force transmit data to mark (the idle condition).
Jamming transmit data to mark created several requirements. The first was that two dummy characters had to be sent to the USART before leaving transmit node. Under ideal conditions these characters were never transmitted. Adding two to the count of characters to be transmitted from a packet to a terminal was rather easy. The difficult part was guaranteeing the timing required by the 9551. Next character request was signalled at the beginning of stop bit transmission. The interrupt could be delayed by interrupt requests from higher priority devices such as network link devices. It was learned the hard way that the USART interrupt which requested transmit mode reset had to be serviced before the centre of stop bit time. At 1200bps it takes 416 usec to transmit half a bit. Given that some interrupts could take more than a 100 usec to process it was difficult to meet this time constraint. The consequence of not meeting it was that when transmit resumed, the start bit of the dummy character got transmitted. This garbled the first character of the subsequent packet.
The problem was solved by replacing the AMD 9551 with the Intel 8251A. The 8251A does not jam transmit data to mark when transmit mode is turned off.
The only serious problem with the USART concerned transmit shutdown. When the contents of a data packet have been sent to a port, it is necessary to shutdown transmission mode. Neither the UART nor the USART have the ability to transmit an invisible idle (ASCII rubout with start bit omitted or set to mark).When the Transmit is disabled, it simply blocked the path from the UART. With the AMD 9551, turning off transmit mode had two effects. One was to disable future character requests. The second effect was to immediately force transmit data to mark (the idle condition).
Jamming transmit data to mark created several requirements. The first was that two dummy characters had to be sent to the USART before leaving transmit node. Under ideal conditions these characters were never transmitted. Adding two to the count of characters to be transmitted from a packet to a terminal was rather easy. The difficult part was guaranteeing the timing required by the 9551. Next character request was signalled at the beginning of stop bit transmission. The interrupt could be delayed by interrupt requests from higher priority devices such as network link devices. It was learned the hard way that the USART interrupt which requested transmit mode reset had to be serviced before the centre of stop bit time. At 1200bps it takes 416 usec to transmit half a bit. Given that some interrupts could take more than a 100 usec to process it was difficult to meet this time constraint. The consequence of not meeting it was that when transmit resumed, the start bit of the dummy character got transmitted. This garbled the first character of the subsequent packet.
The problem was solved by replacing the AMD 9551 with the Intel 8251A. The 8251A does not jam transmit data to mark when transmit mode is turned off.
Programmable communication interface
Asynchronous and synchronous operation
Compatible with 8251,9551
built in Baud Rate Generator
28-pin DIP package
Asynchronous and synchronous operation
Compatible with 8251,9551
built in Baud Rate Generator
28-pin DIP package
Other Types:
PT1472, Western Digital [pdf]UART Receiver
PT1482, Western Digital [pdf]UART Transmitter
INS1671, National Semiconductor [pdf]
Asynchronous/synchronous transmitter/receiver
Up to 1Mb Baud rate.
Replacement for FD1671
40-pin DIP
Up to 1Mb Baud rate.
Replacement for FD1671
40-pin DIP
Compatible with 8250, AY-3-1015
1854, RCA [pdf]AY-5-1013 [pdf]
Universal Asynchronous Receiver/Transmitter
Compatible with TR1602 and 1863
AY-3-1015 [pdf]Compatible with TR1602 and 1863
Compatible with 8250, CDP6402
AY-3-6402 [pdf]TR1602, ??? [pdf]
Compatible with AY-5-1013 and 1863
1863, ??? [pdf]Compatible with AY-5-1013 and TR1602
S1883, ??? [pdf]UART
8250, Intel [pdf]Programmable asynchronous communications
element
Adds or deletes start, stop and parity bits from searial data stream.
Double data buffering.
Programmable baud rate generator.
40-pin DIP
Compatible with AY-3-1015, CDP6402
found on CCS cards
not a widely used part in the late 70s
Adds or deletes start, stop and parity bits from searial data stream.
Double data buffering.
Programmable baud rate generator.
40-pin DIP
Compatible with AY-3-1015, CDP6402
found on CCS cards
not a widely used part in the late 70s
Programmable communication interface
Asynchronous and synchronous operation
built in Baud Rate Generator
28-pin DIP package
6551 [pdf]Asynchronous and synchronous operation
built in Baud Rate Generator
28-pin DIP package
Asynchronous communications interface adapter
Up to 19.2 K Baud rate with internal clock
Up to 125 K Baud with external 16x clock input.
"-1", "-2", "-3" and "-4" suffixes indicate speed of the chip (in MHz).
28-pin DIP
6852, Motorola [pdf]Up to 19.2 K Baud rate with internal clock
Up to 125 K Baud with external 16x clock input.
"-1", "-2", "-3" and "-4" suffixes indicate speed of the chip (in MHz).
28-pin DIP
Synchronous serial data adapter
Up to 1.5 Mhz transmission.
6852 is a 1 MHz speed
68A52 is a 1.5 MHz speed
68B52 is a 2 MHz speed
24-pin DIP
6853, Motorola [pdf]Up to 1.5 Mhz transmission.
6852 is a 1 MHz speed
68A52 is a 1.5 MHz speed
68B52 is a 2 MHz speed
24-pin DIP
Asynchronous communications interface adapter
Transmission rate is up to 19.2 KBaud.
Receive up to transmission rate, or at 16 times of external clock rate.
Full-duplex and half-duplex operations
28-pin DIP
6854, Motorola [pdf]Transmission rate is up to 19.2 KBaud.
Receive up to transmission rate, or at 16 times of external clock rate.
Full-duplex and half-duplex operations
28-pin DIP
Performs CPU/data communication for ADCCP, HDLC and SDLC
standards.
6854 is a 1 MHz speed.
68A54 is a 1.5 MHz speed
68B54 is a 2 MHz speed
28-pin DIP
8274 Dual Uart [pdf]6854 is a 1 MHz speed.
68A54 is a 1.5 MHz speed
68B54 is a 2 MHz speed
28-pin DIP
Z80 SIO, Zilog [pdf]
Z80 DART, Zilog [pdf]
8530, Zilog [pdf]
8531, Zilog [pdf]
NEC7201, NEC, Siemens [pdf]
Multi-protocol serial communication controller
Two full-duplex serial channels.
4 independent DMA channels.
40-pin DIP
TMS5501, TI [pdf]Two full-duplex serial channels.
4 independent DMA channels.
40-pin DIP
TMS6011, TI [pdf]
Here's an additional website which have some good references for UART, USART chips.
ChipDir